This invention relates to an input/output architecture for a programmable logic device, and more particularly to a programmable logic device having a plurality of input/output regions, each capable of supporting input/output standards with different power requirements than the other regions.
Programmable logic devices are well known. Commonly, a programmable logic device has a plurality of substantially identical logic elements, each of which can be programmed to perform certain desired logic functions. The logic elements have access to a programmable interconnect structure that allows a user to interconnect the various logic elements in almost any desired configuration. Finally, the interconnect structure also provides access to a plurality of input/output (xe2x80x9cI/Oxe2x80x9d) pins, with the connections of the pins to the interconnect structure also being programmable and being made through suitable I/O buffer circuitry.
At one time, programmable logic devices of the type just described were implemented almost exclusively using transistor-transistor logic (xe2x80x9cTTLxe2x80x9d), in which a logical xe2x80x9chighxe2x80x9d signal was nominally at 5 volts, while a logical xe2x80x9clowxe2x80x9d signal was nominally at ground potential, or 0 volts. More recently, however, other logic standards have come into general use, some of which use different signalling schemes, such as LVTTL (Low Voltage TTL, which exists in a 3.3-volt version or a 2.5-volt version), PCI (Peripheral Component Interface, which requires 3.3-volt power supply), SSTL (Series Stub Terminated Logic, which has several variants), GTL (Gunning Transceiver Logic) or GTL+, HSTL (High Speed Transceiver Logic, which has several variants), LVDS (Low Voltage Differential Signalling), and others. Not only might these signalling schemes use different voltage levels for a xe2x80x9chighxe2x80x9d signal, and therefore require different supply voltages (the power supply requirements for these various standards may be 5.0 volts, 3.3 volts, 2.7 volts, 2.5 volts, 1.8 volts or 1.5 volts), but some of them, such as GTL/GTL+, various variants of SSTL and HSTL, and other standards such as CTT, ECL and 3.3V AGP, may require a source of reference voltage. Typically, like the supply voltage, reference voltage would be supplied externally, using one of the I/O pins.
Power for the circuitry on the programmable logic device is typically supplied by a power bus that extends over the entire device. Heretofore, that same power bus supplied power to all of the I/O circuitry as well. Similarly, if a reference voltage were needed, a reference voltage bus would be provided on the device to supply all of the circuitry that required the reference voltage.
There is no inherent reason why two or more different I/O standards could not be used on one programmable logic device, with some I/O pins driven by circuitry compatible with one standard and other I/O pins driven by circuitry compatible with a different standard. However, the known single supply voltage bus and single reference voltage bus (if multiple reference voltages are needed) would be unable to supply more than one such standard or, at best, would only be able to supply multiple standards all of which had the same power requirements.
It would be desirable to be able to provide a programmable logic device that programmably supports a plurality of I/O standards, at least two of those standards being supportable simultaneously.
It would further be desirable to be able to provide such a programmable logic device in which the plurality of I/O standard; could have different power requirements which could be met simultaneously by the programmable logic device.
It is an object of this invention to attempt to provide a programmable logic device that programmably supports a plurality of I/O standards, at least two of those standards being supportable simultaneously.
It is a further object of this invention to attempt to provide such a programmable logic device in which the plurality of I/O standards could have different power requirements which could be met simultaneously by the programmable logic device.
In accordance with the present invention, there is provided an input/output structure for a programmable logic device that accommodates a plurality of logic signalling standards having differing power requirements. The input/output structure has a plurality of input/output terminals, and a plurality of input/output circuits associated with that plurality of input/output terminals. Each of the input/output circuits programmably accommodates at least some of the plurality of logic signalling standards and is coupled to a respective one of the input/output terminals for buffering input/output signals between that respective one of the input/output terminals and the programmable logic device. The input/output structure also has a plurality of power bus conductors, and each of the power bus conductors is spatially disposed adjacent a respective subset of the plurality of input/output circuits. When circuits in each respective subset of the plurality of input/output buffers are programmably configured for one of the plurality of logic signalling standards, a respective power bus conductor adjacent each respective subset provides power compatible with power requirements of that one of the standards for which circuits in the respective subset are configured.
In a programmable logic device, or other integrated circuit, which supports a variety of logic signalling standards, each of which may have different power requirements and some of which may require voltage references, an I/O structure can be provided that allows more than one of those logic signalling standards to be used at the same time on the programmable logic device or other integrated circuit. Specifically, in accordance with the invention, an I/O circuit can be provided at each I/O terminal or pin that is capable of handling all of the different kinds of logic signalling standards, with the standard used at a particular terminal chosen by suitably programming the associated I/O circuit. However, instead of providing a single power supply bus for all of the I/O circuits and a single reference supply bus for all of the I/O circuits (assuming that at least one of the logic signalling standards requires a reference voltage), the I/O circuits are broken down into groups, with each group served by its own power bus and its own reference bus. Each respective one of these buses has its own associated I/O pin at which the user supplies the correct supply or reference voltage for the logic signalling standard he has chosen to use at the group of I/O terminals served by those respective supply and reference buses. Preferably, all members of a particular group of I/O circuits served by a particular set of power and reference buses are spatially near one another. It is also possible for the I/O circuits in the group to be spread around the programmable logic device or other integrated circuit, although there is a penalty paid in die area or xe2x80x9creal estatexe2x80x9d because the buses must run all over the device instead of being limited to a compact area. Similarly, it is also within the scope of the invention to have independent power buses, and reference buses (if appropriate), for each standard running to all I/O circuits on the device, or at least to I/O circuits in all areas of the device, although there is also a xe2x80x9creal estatexe2x80x9d penalty in such an embodiment.
In a particularly preferred embodiment, not all I/O circuits can handle all of the various logic signalling standards used on the device. Specifically, because of the particularly different requirements of Low Voltage Differential Signalling (LVDS), the LVDS circuits are separate from the other types of I/O circuits. Indeed, the input and output requirements of LVDS are so different that preferably there are separate LVDS input circuits (which preferably actually can handle all types of inputs, and also all types of outputs except LVDS outputs), and separate LVDS output circuits (which preferably can handle all kinds of outputs and all types of inputs except LVDS inputs).
I/O pins on programmable logic devices and other integrated circuits are typically provided at the edge of the device. Therefore, in accordance with the present invention, the difference groups or blocks of I/O circuits served by the different power and reference buses are typically arranged as blocks of adjacent I/O circuits along the device edge. Each block preferably has a power bus and a reference bus running alongside it, substantially parallel to the device edge. Each bus preferably runs in the same place relative to its associated block that other buses occupy relative to their respective blocks. This conserves die area on the device, because a single bus or pair of buses can be provided, which is then segmented at the boundaries of the various blocks to create the independent buses.
Alternatively, the device may be constructed using bump array technology, which is well known, where the I/O terminals may be anywhere on the surface of the device and are contacted by suitable bumps on a contact plane parallel to the device surface. In such a device, the various I/O circuits still are preferably grouped together spatially, so that the bumps used to provide the power and reference voltages to circuits using identical standards can be ganged or banked together.
Moreover, while an individual I/O circuit can only be configured for one standard in any given configuration of the programmable logic device, it is not necessary for all I/O circuits in a particular block according to this invention to be configured the same way. It is only necessary that all I/O circuits in the block be configured to have the same power requirements, because only one power supply voltage can be provided to the block. Similarly, if some I/O circuits in a block need a reference voltage, it is only necessary that all I/O circuits in the block that need a reference voltage need the same reference voltage. It is even possible to have different I/O circuits in the block, all of which have the same power supply voltage requirements, but only some of which require a reference voltage at all. As long as those circuits that do not require a reference voltage use the same power supply voltage, they simply ignore the reference voltage bus. Moreover, it is also possible to have an output circuit that does not require a power supply voltage (GTL/GTL+ pull to ground for a logic xe2x80x9clowxe2x80x9d and simply do not drive the output for a logic xe2x80x9chighxe2x80x9d), but does require a reference voltage, and such a circuit can be included in a block with other circuits requiring the same reference voltage, regardless of the power supply voltage in that block, which the circuit will simply ignore.